# Extended Page Tables (EPT) Architecture reference: Feex Also called VT-x with EPT EPT, Extended Page Tables, provides a second stage of memory translation for Intel virtual machines. A VT-x with EPT label describes both virtualization and this additional translation facility. ## What you need to know EPT, Extended Page Tables, provides a second stage of memory translation for Intel virtual machines. A VT-x with EPT label describes both virtualization and this additional translation facility. ## How it works The guest's page tables translate guest virtual addresses to guest physical addresses; EPT translates guest physical addresses to host physical addresses under hypervisor control. EPT entries have their own permissions and can produce EPT violations when a mapping or access is disallowed. Translation caches and invalidation rules remain part of correctness. ## Where it is useful A hypervisor can map each VM's guest-physical memory to its assigned host pages while allowing the guest to manage its own virtual address space. This can reduce reliance on older shadow-page-table techniques, but actual workload cost still depends on translation caching and access patterns. ## How to check support and enablement Check VMX controls and the EPT capability information through the hypervisor or privileged platform tooling. VT-x's CPUID bit alone is insufficient. Verify the exact controls and page sizes required by the deployment rather than treating EPT as a single universal mode. A virtualized deployment has several layers: physical capability, firmware permission, the active host hypervisor, exposed guest capabilities and guest OS support. Check the layer where the operation actually runs, including nested virtualization when relevant. ## What the feature does not establish EPT is not VT-d: CPU-originated guest memory translation and device DMA remapping are different paths. EPT support does not imply every EPT page size, execute-control extension or nested-virtualization configuration. ## Compatibility and performance in practice CPU execution, guest memory translation and device DMA remapping are separate facilities. Do not infer passthrough or isolation from one virtualization field. Use the hypervisor's supported diagnostics and exact platform/device requirements. ## A practical verification checklist 1. Record the exact processor or platform model and the application, OS and runtime versions involved. Preserve the wording of the actual error or requirement. 2. Check the manufacturer reference for that exact model, then inspect the effective capability and enabled state in the environment where the program runs. 3. Compare every requirement of the selected binary or backend. A similarly named feature, alias or broad technology label is not enough. 4. Confirm the application selected the intended implementation. Use its documented diagnostics and a supported fallback when requirements are not met. 5. Make one supported change at a time and repeat the same workload. Keep the original configuration and recovery path available. ## If the feature is listed but software cannot use it Start with the exact failing component. A hardware database describes recorded capability; the operating system or hypervisor can expose a different effective environment. An illegal-instruction error also needs investigation of the actual faulting instruction and binary build, because corruption or an unrelated unsupported instruction can produce a similar symptom. Install the application, driver or runtime version supported for the exact platform, and use the vendor's documented baseline or fallback build if needed. A software update cannot create an instruction that the processor lacks. Firmware and security-policy changes should follow the system manufacturer's procedure and a recovery plan rather than a generic optimization recipe. ## Related features and useful distinctions [VT-x](https://feex.it/wiki/hardware/system/vt-x/) · [Second-Level Address Translation](https://feex.it/wiki/hardware/system/slat/) · [NPT and RVI](https://feex.it/wiki/hardware/system/npt-rvi/) · [VT-d](https://feex.it/wiki/hardware/system/vt-d/) · [Mode-Based Execute Control](https://feex.it/wiki/hardware/system/mode-based-execute-control/) ## Sources and scope of this explanation [Intel 64 and IA-32 Architectures Software Developer's Manual](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html) These references establish architectural behavior and software requirements. They do not independently verify every feature value on a linked hardware model page. For model support, use that page's manufacturer evidence and check the effective system configuration. This article does not supply a benchmark, certification or independent review date. ## Related These entities connect to this article. Type is shown on every link. [VT-x: Architecture reference](https://feex.it/wiki/hardware/system/vt-x/)[Second-Level Address Translation: Architecture reference](https://feex.it/wiki/hardware/system/slat/)[NPT and RVI: Architecture reference](https://feex.it/wiki/hardware/system/npt-rvi/)[VT-d: Architecture reference](https://feex.it/wiki/hardware/system/vt-d/)[Mode-Based Execute Control: Architecture reference](https://feex.it/wiki/hardware/system/mode-based-execute-control/) ## Sources and verification Editorial ownership: Feex. No independent review date is recorded. [How we research](https://feex.it/wiki/research/). - [Intel 64 and IA-32 Architectures Software Developer's Manual ](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html)· Volumes 1 and 2 describe the named instruction families and CPUID; Volume 3 describes state, paging, VMX and protection controls. Architecture documentation does not establish support for a particular model. [Report a correction to Feex](https://feex.it/contact/) ## Was this article useful? A yes or no is enough. Pick a reason if you want, or add a short note. Quick facts The short identity of this page. Specs, sources, and the full story stay in the article. --- Source: [Canonical Feex Wiki page](https://feex.it/wiki/hardware/system/ept/) [Developer guide](https://feex.it/wiki/developers/) | [API policy](https://feex.it/developers/api-policy/) | [Agent guidance](https://feex.it/wiki/llms.txt)