# Second-Level Address Translation Architecture reference: Feex Second-Level Address Translation, SLAT, is a general term for hardware-assisted translation from guest physical to host physical addresses. Intel EPT and AMD NPT provide vendor-specific implementations. ## What you need to know Second-Level Address Translation, SLAT, is a general term for hardware-assisted translation from guest physical to host physical addresses. Intel EPT and AMD NPT provide vendor-specific implementations. ## How it works A guest's own page tables describe its virtual memory. A second mapping controlled by the hypervisor associates the resulting guest physical addresses with host memory and access permissions. The processor combines the stages under the architecture's translation and caching rules. ## Where it is useful A hypervisor can avoid maintaining some forms of shadow page tables and instead let hardware perform the staged walk. The remaining overhead depends on page size, nested-walk caching, TLB behavior and guest memory locality. ## How to check support and enablement Identify the processor vendor and check the corresponding EPT or NPT capability through the hypervisor's supported diagnostics. Check the complete requirements of the feature being deployed, including firmware and OS support. A virtualized deployment has several layers: physical capability, firmware permission, the active host hypervisor, exposed guest capabilities and guest OS support. Check the layer where the operation actually runs, including nested virtualization when relevant. ## What the feature does not establish SLAT is not a separate universal CPUID bit, a replacement for IOMMU or proof of support for a particular OS virtualization product. A generic SLAT field needs a vendor-specific interpretation and does not establish every advanced translation feature. ## Compatibility and performance in practice CPU execution, guest memory translation and device DMA remapping are separate facilities. Do not infer passthrough or isolation from one virtualization field. Use the hypervisor's supported diagnostics and exact platform/device requirements. ## A practical verification checklist 1. Record the exact processor or platform model and the application, OS and runtime versions involved. Preserve the wording of the actual error or requirement. 2. Check the manufacturer reference for that exact model, then inspect the effective capability and enabled state in the environment where the program runs. 3. Compare every requirement of the selected binary or backend. A similarly named feature, alias or broad technology label is not enough. 4. Confirm the application selected the intended implementation. Use its documented diagnostics and a supported fallback when requirements are not met. 5. Make one supported change at a time and repeat the same workload. Keep the original configuration and recovery path available. ## If the feature is listed but software cannot use it Start with the exact failing component. A hardware database describes recorded capability; the operating system or hypervisor can expose a different effective environment. An illegal-instruction error also needs investigation of the actual faulting instruction and binary build, because corruption or an unrelated unsupported instruction can produce a similar symptom. Install the application, driver or runtime version supported for the exact platform, and use the vendor's documented baseline or fallback build if needed. A software update cannot create an instruction that the processor lacks. Firmware and security-policy changes should follow the system manufacturer's procedure and a recovery plan rather than a generic optimization recipe. ## Related features and useful distinctions [Extended Page Tables (EPT)](https://feex.it/wiki/hardware/system/ept/) · [NPT and RVI](https://feex.it/wiki/hardware/system/npt-rvi/) · [VT-x](https://feex.it/wiki/hardware/system/vt-x/) · [AMD-V and SVM](https://feex.it/wiki/hardware/system/amd-v/) ## Sources and scope of this explanation [Intel 64 and IA-32 Architectures Software Developer's Manual](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html) · [AMD64 Architecture Programmer's Manual, Volume 2: System Programming](https://docs.amd.com/v/u/en-US/24593_3.46_APM_Vol2) These references establish architectural behavior and software requirements. They do not independently verify every feature value on a linked hardware model page. For model support, use that page's manufacturer evidence and check the effective system configuration. This article does not supply a benchmark, certification or independent review date. ## Related These entities connect to this article. Type is shown on every link. [Extended Page Tables (EPT): Architecture reference](https://feex.it/wiki/hardware/system/ept/)[NPT and RVI: Architecture reference](https://feex.it/wiki/hardware/system/npt-rvi/)[VT-x: Architecture reference](https://feex.it/wiki/hardware/system/vt-x/)[AMD-V and SVM: Architecture reference](https://feex.it/wiki/hardware/system/amd-v/) ## Sources and verification Editorial ownership: Feex. No independent review date is recorded. [How we research](https://feex.it/wiki/research/). - [Intel 64 and IA-32 Architectures Software Developer's Manual ](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html)· Volumes 1 and 2 describe the named instruction families and CPUID; Volume 3 describes state, paging, VMX and protection controls. Architecture documentation does not establish support for a particular model. - [AMD64 Architecture Programmer's Manual, Volume 2: System Programming ](https://docs.amd.com/v/u/en-US/24593_3.46_APM_Vol2)· System programming, SVM and nested translation, revision 3.46. The current documentation viewer requires JavaScript; older document URLs may have been retired. [Report a correction to Feex](https://feex.it/contact/) ## Was this article useful? A yes or no is enough. Pick a reason if you want, or add a short note. Quick facts The short identity of this page. Specs, sources, and the full story stay in the article. --- Source: [Canonical Feex Wiki page](https://feex.it/wiki/hardware/system/slat/) [Developer guide](https://feex.it/wiki/developers/) | [API policy](https://feex.it/developers/api-policy/) | [Agent guidance](https://feex.it/wiki/llms.txt)