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CMPXCHG16B

Architecture referenceFeex

CMPXCHG16B compares and conditionally exchanges a 16-byte memory value using a defined register-pair interface. Correct alignment and atomicity requirements are essential for concurrent use.

What you need to know

CMPXCHG16B compares and conditionally exchanges a 16-byte memory value using a defined register-pair interface. Correct alignment and atomicity requirements are essential for concurrent use.

How it works

The instruction compares a 128-bit memory operand with the expected value in RDX:RAX, then conditionally stores RCX:RBX or loads the observed memory value into the expected-value registers. The memory operand must satisfy its 16-byte alignment requirement. Shared-memory atomic use requires the appropriate LOCK semantics.

Where it is useful

A runtime can use the instruction for an atomic update of a tagged pointer or pair of machine words. The compiler's atomic API also accounts for memory ordering, type alignment and fallback behavior; hand-written assembly must satisfy all of those contracts.

How to check support and enablement

CPUID.01H:ECX bit 13 indicates CMPXCHG16B. Check the ABI and runtime's atomic guarantees as well as the hardware bit. Use the language's supported atomic query when deciding whether an operation is lock-free.

Check the exact instruction and operand form rather than inferring support from a neighboring extension. Scalar integer features generally use general-purpose registers; an encoding associated with vectors does not automatically mean a vector-state requirement.

What the feature does not establish

The instruction is not a general 128-bit arithmetic unit, and its presence does not mean every language's 128-bit atomic type is lock-free in every build. Misalignment can fault even on a supported CPU.

Compatibility and performance in practice

Correctness depends on edge cases as well as speed. Zero input, overflow, carry flags, operand width, alignment and memory ordering can change semantics. Prefer compiler or library interfaces that document these details and provide a supported fallback.

A practical verification checklist

  1. Record the exact processor or platform model and the application, OS and runtime versions involved. Preserve the wording of the actual error or requirement.
  2. Check the manufacturer reference for that exact model, then inspect the effective capability and enabled state in the environment where the program runs.
  3. Compare every requirement of the selected binary or backend. A similarly named feature, alias or broad technology label is not enough.
  4. Confirm the application selected the intended implementation. Use its documented diagnostics and a supported fallback when requirements are not met.
  5. Make one supported change at a time and repeat the same workload. Keep the original configuration and recovery path available.

If the feature is listed but software cannot use it

Start with the exact failing component. A hardware database describes recorded capability; the operating system or hypervisor can expose a different effective environment. An illegal-instruction error also needs investigation of the actual faulting instruction and binary build, because corruption or an unrelated unsupported instruction can produce a similar symptom.

Install the application, driver or runtime version supported for the exact platform, and use the vendor's documented baseline or fallback build if needed. A software update cannot create an instruction that the processor lacks. Firmware and security-policy changes should follow the system manufacturer's procedure and a recovery plan rather than a generic optimization recipe.

Sources and scope of this explanation

Intel 64 and IA-32 Architectures Software Developer's Manual · x86-64 psABI: processor architecture and microarchitecture levels

These references establish architectural behavior and software requirements. They do not independently verify every feature value on a linked hardware model page. For model support, use that page's manufacturer evidence and check the effective system configuration. This article does not supply a benchmark, certification or independent review date.

Sources and verification

Editorial ownership: Feex. No independent review date is recorded. How we research.

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