Execute Disable (NX)
Execute Disable, also called NX or XD in x86 terminology, allows page tables to mark memory as non-executable. It is a hardware building block used by operating-system execution-protection policies.
What you need to know
Execute Disable, also called NX or XD in x86 terminology, allows page tables to mark memory as non-executable. It is a hardware building block used by operating-system execution-protection policies.
How it works
When enabled in the applicable paging environment, an instruction fetch from a page marked non-executable faults instead of executing its bytes. Page permissions distinguish execution from data access; software is responsible for assigning suitable permissions and handling transitions for legitimate generated code.
Where it is useful
An OS can map a data buffer without execution permission so writing machine-code bytes into that buffer does not make it an executable code page. JIT runtimes use documented memory-management APIs and permission policies for generated code.
How to check support and enablement
CPUID.80000001H:EDX bit 20 enumerates the x86 execute-disable capability under the relevant vendor definition. Actual enforcement also depends on the paging mode and OS enablement. Inspect the OS's documented protection status rather than inferring it from a CPU model.
Capability, enablement and enforcement must be checked separately. A processor can support a protection while the OS, application or virtual-machine policy does not activate it. A database support field is not an attestation of a running system.
What the feature does not establish
NX does not establish that an executable file is safe, block every code-reuse attack or prove Windows eligibility. Data remains readable or writable according to separate permissions. A feature flag does not mean every memory mapping follows a strict write/execute policy.
Compatibility and performance in practice
Keep the OS, firmware and affected runtime current. If a protection exposes a compatibility problem, use vendor diagnostics and supported updates first. A broad protection toggle can affect unrelated applications and should follow an explicit deployment and recovery policy.
A practical verification checklist
- Record the exact processor or platform model and the application, OS and runtime versions involved. Preserve the wording of the actual error or requirement.
- Check the manufacturer reference for that exact model, then inspect the effective capability and enabled state in the environment where the program runs.
- Compare every requirement of the selected binary or backend. A similarly named feature, alias or broad technology label is not enough.
- Confirm the application selected the intended implementation. Use its documented diagnostics and a supported fallback when requirements are not met.
- Make one supported change at a time and repeat the same workload. Keep the original configuration and recovery path available.
If the feature is listed but software cannot use it
Start with the exact failing component. A hardware database describes recorded capability; the operating system or hypervisor can expose a different effective environment. An illegal-instruction error also needs investigation of the actual faulting instruction and binary build, because corruption or an unrelated unsupported instruction can produce a similar symptom.
Install the application, driver or runtime version supported for the exact platform, and use the vendor's documented baseline or fallback build if needed. A software update cannot create an instruction that the processor lacks. Firmware and security-policy changes should follow the system manufacturer's procedure and a recovery plan rather than a generic optimization recipe.
Sources and scope of this explanation
Intel 64 and IA-32 Architectures Software Developer's Manual
These references establish architectural behavior and software requirements. They do not independently verify every feature value on a linked hardware model page. For model support, use that page's manufacturer evidence and check the effective system configuration. This article does not supply a benchmark, certification or independent review date.
Sources and verification
Editorial ownership: Feex. No independent review date is recorded. How we research.
- Intel 64 and IA-32 Architectures Software Developer's Manual · Volumes 1 and 2 describe the named instruction families and CPUID; Volume 3 describes state, paging, VMX and protection controls. Architecture documentation does not establish support for a particular model.
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