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Invariant TSC

Architecture referenceFeex

Invariant TSC describes a time-stamp counter whose rate remains constant across the architectural power and frequency states covered by the feature. It is not a direct measurement of current core frequency.

What you need to know

Invariant TSC describes a time-stamp counter whose rate remains constant across the architectural power and frequency states covered by the feature. It is not a direct measurement of current core frequency.

How it works

The time-stamp counter increments at a platform-defined rate. Invariant behavior separates that rate from changes in the core's operating frequency. Converting ticks to elapsed time requires a valid frequency reference, while comparing values across processors or virtual machines also requires synchronization and virtualization guarantees.

Where it is useful

A runtime may use a suitable counter as part of its high-resolution timing implementation. Dividing a short workload's counter difference by a nominal CPU GHz value can be wrong because TSC rate and executing-core frequency are different quantities.

How to check support and enablement

CPUID.80000007H:EDX bit 8 enumerates invariant TSC under the relevant architecture definition. Prefer the operating system's supported monotonic clock for ordinary timing, because it can account for platform and virtualization policy.

Choose a clock according to the question: elapsed time, thread CPU time and cycles are different measurements. The operating system's clock interfaces incorporate platform policy that a raw instruction sample may bypass.

What the feature does not establish

Invariant does not by itself establish synchronization across sockets, monotonic behavior across VM migration, serialization around measured instructions or the absence of scheduling delays. A raw counter sample is not a CPU utilization percentage.

Compatibility and performance in practice

A benchmark also needs correct compiler boundaries, warmup, representative data and an understanding of migration and scheduling. Repeating a poorly ordered measurement does not make it accurate. Report the environment and uncertainty with any result.

A practical verification checklist

  1. Record the exact processor or platform model and the application, OS and runtime versions involved. Preserve the wording of the actual error or requirement.
  2. Check the manufacturer reference for that exact model, then inspect the effective capability and enabled state in the environment where the program runs.
  3. Compare every requirement of the selected binary or backend. A similarly named feature, alias or broad technology label is not enough.
  4. Confirm the application selected the intended implementation. Use its documented diagnostics and a supported fallback when requirements are not met.
  5. Make one supported change at a time and repeat the same workload. Keep the original configuration and recovery path available.

If the feature is listed but software cannot use it

Start with the exact failing component. A hardware database describes recorded capability; the operating system or hypervisor can expose a different effective environment. An illegal-instruction error also needs investigation of the actual faulting instruction and binary build, because corruption or an unrelated unsupported instruction can produce a similar symptom.

Install the application, driver or runtime version supported for the exact platform, and use the vendor's documented baseline or fallback build if needed. A software update cannot create an instruction that the processor lacks. Firmware and security-policy changes should follow the system manufacturer's procedure and a recovery plan rather than a generic optimization recipe.

Sources and scope of this explanation

Intel 64 and IA-32 Architectures Software Developer's Manual

These references establish architectural behavior and software requirements. They do not independently verify every feature value on a linked hardware model page. For model support, use that page's manufacturer evidence and check the effective system configuration. This article does not supply a benchmark, certification or independent review date.

Sources and verification

Editorial ownership: Feex. No independent review date is recorded. How we research.

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