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BMI2

Architecture referenceFeex

BMI2 adds scalar x86 bit and integer operations such as parallel bit deposit/extract, variable shifts and flag-independent multiplication. It is separate from BMI1.

What you need to know

BMI2 adds scalar x86 bit and integer operations such as parallel bit deposit/extract, variable shifts and flag-independent multiplication. It is separate from BMI1.

How it works

PEXT gathers selected input bits into a dense low-order result; PDEP scatters low-order input bits to positions selected by a mask. Other BMI2 instructions include BZHI, MULX, RORX, SHLX, SHRX and SARX. These operate on scalar integer registers despite using VEX encoding.

Where it is useful

A compact board representation or bitfield codec can use PEXT/PDEP to map between dense and sparse bit layouts. Their execution cost varies substantially between implementations, so an algorithm should benchmark representative inputs rather than assume a short instruction sequence is fast.

How to check support and enablement

CPUID.07H.00H:EBX bit 8 enumerates BMI2. Check the target-specific performance of the instructions actually used and keep dispatch outside code compiled to require unsupported features.

Check the exact instruction and operand form rather than inferring support from a neighboring extension. Scalar integer features generally use general-purpose registers; an encoding associated with vectors does not automatically mean a vector-state requirement.

What the feature does not establish

BMI2 is not an AVX vector extension and does not require YMM state merely because the encoding is VEX. It does not establish ADX or BMI1. MULX and conventional multiplication differ in register and flag behavior.

Compatibility and performance in practice

Correctness depends on edge cases as well as speed. Zero input, overflow, carry flags, operand width, alignment and memory ordering can change semantics. Prefer compiler or library interfaces that document these details and provide a supported fallback.

A practical verification checklist

  1. Record the exact processor or platform model and the application, OS and runtime versions involved. Preserve the wording of the actual error or requirement.
  2. Check the manufacturer reference for that exact model, then inspect the effective capability and enabled state in the environment where the program runs.
  3. Compare every requirement of the selected binary or backend. A similarly named feature, alias or broad technology label is not enough.
  4. Confirm the application selected the intended implementation. Use its documented diagnostics and a supported fallback when requirements are not met.
  5. Make one supported change at a time and repeat the same workload. Keep the original configuration and recovery path available.

If the feature is listed but software cannot use it

Start with the exact failing component. A hardware database describes recorded capability; the operating system or hypervisor can expose a different effective environment. An illegal-instruction error also needs investigation of the actual faulting instruction and binary build, because corruption or an unrelated unsupported instruction can produce a similar symptom.

Install the application, driver or runtime version supported for the exact platform, and use the vendor's documented baseline or fallback build if needed. A software update cannot create an instruction that the processor lacks. Firmware and security-policy changes should follow the system manufacturer's procedure and a recovery plan rather than a generic optimization recipe.

Sources and scope of this explanation

Intel 64 and IA-32 Architectures Software Developer's Manual · x86-64 psABI: processor architecture and microarchitecture levels

These references establish architectural behavior and software requirements. They do not independently verify every feature value on a linked hardware model page. For model support, use that page's manufacturer evidence and check the effective system configuration. This article does not supply a benchmark, certification or independent review date.

Sources and verification

Editorial ownership: Feex. No independent review date is recorded. How we research.

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