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LZCNT

Architecture referenceFeex

LZCNT counts leading zero bits in an integer operand. It differs from BSR, including its result for zero, and requires an explicit capability check.

What you need to know

LZCNT counts leading zero bits in an integer operand. It differs from BSR, including its result for zero, and requires an explicit capability check.

How it works

The result is the number of zero bits preceding the highest set bit in the chosen operand width. For an all-zero operand, LZCNT returns the operand width. Its flags and zero behavior are defined differently from the older bit-scan-reverse operation with a related encoding.

Where it is useful

A compression or numeric-format routine can use the count to determine how many significant bits a value needs. Correct handling of zero is necessary for size calculations and shifts, because a mistaken bit-scan substitution can produce an invalid result.

How to check support and enablement

CPUID.80000001H:ECX bit 5 enumerates LZCNT under the relevant vendor definition. Verify that the extended leaf exists first. Use a supported compiler/runtime feature query and a fallback whose zero semantics match.

Check the exact instruction and operand form rather than inferring support from a neighboring extension. Scalar integer features generally use general-purpose registers; an encoding associated with vectors does not automatically mean a vector-state requirement.

What the feature does not establish

LZCNT does not count all set bits and is not TZCNT. An unsupported processor may interpret the encoding as BSR, so simply trying the instruction is an unsafe feature test. BMI1 and BMI2 are separate capabilities.

Compatibility and performance in practice

Correctness depends on edge cases as well as speed. Zero input, overflow, carry flags, operand width, alignment and memory ordering can change semantics. Prefer compiler or library interfaces that document these details and provide a supported fallback.

A practical verification checklist

  1. Record the exact processor or platform model and the application, OS and runtime versions involved. Preserve the wording of the actual error or requirement.
  2. Check the manufacturer reference for that exact model, then inspect the effective capability and enabled state in the environment where the program runs.
  3. Compare every requirement of the selected binary or backend. A similarly named feature, alias or broad technology label is not enough.
  4. Confirm the application selected the intended implementation. Use its documented diagnostics and a supported fallback when requirements are not met.
  5. Make one supported change at a time and repeat the same workload. Keep the original configuration and recovery path available.

If the feature is listed but software cannot use it

Start with the exact failing component. A hardware database describes recorded capability; the operating system or hypervisor can expose a different effective environment. An illegal-instruction error also needs investigation of the actual faulting instruction and binary build, because corruption or an unrelated unsupported instruction can produce a similar symptom.

Install the application, driver or runtime version supported for the exact platform, and use the vendor's documented baseline or fallback build if needed. A software update cannot create an instruction that the processor lacks. Firmware and security-policy changes should follow the system manufacturer's procedure and a recovery plan rather than a generic optimization recipe.

Sources and scope of this explanation

Intel 64 and IA-32 Architectures Software Developer's Manual · AMD CPUID Specification, publication 25481 · x86-64 psABI: processor architecture and microarchitecture levels

These references establish architectural behavior and software requirements. They do not independently verify every feature value on a linked hardware model page. For model support, use that page's manufacturer evidence and check the effective system configuration. This article does not supply a benchmark, certification or independent review date.

Sources and verification

Editorial ownership: Feex. No independent review date is recorded. How we research.

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