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CET-IBT

Architecture referenceFeex

CET-IBT is indirect branch tracking, a control-flow protection that checks the targets of tracked indirect calls and jumps. It is separate from CET shadow stacks.

What you need to know

CET-IBT is indirect branch tracking, a control-flow protection that checks the targets of tracked indirect calls and jumps. It is separate from CET shadow stacks.

How it works

When tracking is enabled for the applicable execution environment, an indirect transfer must reach an appropriate ENDBR landing instruction under the architecture's rules. The mechanism uses architectural tracking state and raises a control-protection exception when the contract is violated. Compiler and binary instrumentation are part of deployment.

Where it is useful

A compiler can mark valid indirect-entry locations in a library. The OS and runtime must apply compatible enablement and policy to the code that executes. Seeing ENDBR bytes in a disassembly does not, by itself, prove the system currently enforces IBT.

How to check support and enablement

CPUID.07H.00H:EDX bit 20 enumerates IBT capability. Check the OS's user/supervisor support and binary policy separately. Diagnose compatibility using official compiler and OS guidance rather than removing landing instructions from a binary.

Capability, enablement and enforcement must be checked separately. A processor can support a protection while the OS, application or virtual-machine policy does not activate it. A database support field is not an attestation of a running system.

What the feature does not establish

IBT does not check ordinary function returns in the way shadow stacks do. It is not a guarantee of complete control-flow integrity or application safety, and support for shadow stacks does not establish IBT support.

Compatibility and performance in practice

Keep the OS, firmware and affected runtime current. If a protection exposes a compatibility problem, use vendor diagnostics and supported updates first. A broad protection toggle can affect unrelated applications and should follow an explicit deployment and recovery policy.

A practical verification checklist

  1. Record the exact processor or platform model and the application, OS and runtime versions involved. Preserve the wording of the actual error or requirement.
  2. Check the manufacturer reference for that exact model, then inspect the effective capability and enabled state in the environment where the program runs.
  3. Compare every requirement of the selected binary or backend. A similarly named feature, alias or broad technology label is not enough.
  4. Confirm the application selected the intended implementation. Use its documented diagnostics and a supported fallback when requirements are not met.
  5. Make one supported change at a time and repeat the same workload. Keep the original configuration and recovery path available.

If the feature is listed but software cannot use it

Start with the exact failing component. A hardware database describes recorded capability; the operating system or hypervisor can expose a different effective environment. An illegal-instruction error also needs investigation of the actual faulting instruction and binary build, because corruption or an unrelated unsupported instruction can produce a similar symptom.

Install the application, driver or runtime version supported for the exact platform, and use the vendor's documented baseline or fallback build if needed. A software update cannot create an instruction that the processor lacks. Firmware and security-policy changes should follow the system manufacturer's procedure and a recovery plan rather than a generic optimization recipe.

Sources and scope of this explanation

Intel 64 and IA-32 Architectures Software Developer's Manual · Linux kernel: Control-flow Enforcement Technology shadow stack

These references establish architectural behavior and software requirements. They do not independently verify every feature value on a linked hardware model page. For model support, use that page's manufacturer evidence and check the effective system configuration. This article does not supply a benchmark, certification or independent review date.

Sources and verification

Editorial ownership: Feex. No independent review date is recorded. How we research.

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